The present invention concerns a graphics controller for a computer, and more specifically, a method and apparatus for providing for efficient use of a memory within a data frame buffer to reduce refresh bandwidth for a video display.
In a computer display system in which a graphics controller is used in the display of information on a video monitor, a video display mode defines the transformations required to convert the contents of frame buffer memory of a graphics device into pixel data that can be displayed by a monitor. The simplest display modes directly read the red, green, and blue intensity values of the pixel from the frame buffer, while more complex display modes may perform several frame buffer accesses for each pixel or set of pixels.
One classic example of a complex video display mode is the text mode of the Video Graphics Array (VGA) controller commonly found in the Personal Computer (PC) marketplace. For example, the frame buffer memory in a standard VGA controller configured for text mode operation may typically be configured so that four maps each contain 64K bytes. The VGA controller accesses the four maps in parallel, reading or writing one byte from each map with each memory access. The first map (Map 0) contains ASCII eight bit character codes. The second map (Map 1) contains attribute bytes for the corresponding ASCII character. The attribute byte for each character specifies properties such as color, blinking, and underline. The third map (Map 2) contains a font table. The ASCII eight bit characters codes stored in Map 0 are an index into the font table in Map 2. The font table includes scan line information for each ASCII character. For a typical prior art application, the ASCII eight bit character codes in Map 0 and the associated attribute bytes in Map 1 take up only 16K bytes. Thus the upper 48K of maps 0 and 1 are unused in the text modes. The fourth map (Map 3) also is unused.
In the prior art, a typical VGA controller performs the following actions to produce a displayable image on a monitor (i.e. during screen refresh). First, the VGA controller reads an ASCII/attribute pair from Map 0 and Map 1 in memory. Next, the VGA controller uses the ASCII value obtained from Map 0 and row scan number to compute an address into the font memory map. The row scan number comes from the CRT controller (monitor timing generator). This is used to read a one byte font line from the font table in Map 2. The font line is equivalent to one scan line of the character. Finally, the 8 bits of font lines from the font table in Map 2 is translated into 8 or 9 pixels based on attribute, ASCII value, and controller configuration. In the 9 pixel wide font modes, the ninth pixel is formed by replicating the eighth pixel for ASCII values in a given range, otherwise the ninth pixel is set to the background color.
One key advantage to this standard VGA implementation is the density of information storage. Each character requires only two bytes of storage, regardless of the height of the font. The standard VGA provides access to 16K characters, for a total of 32 KB of memory. The font line information requires N bytes per character, where N is the height of a character. In the standard VGA, the font line information is capable of describing eight character sets of 256 characters each, 32 scan lines high for requiring a total of 64 kilobytes (KB) of storage (8 character sets times 256 characters per character set times 32 bytes per character).
One major disadvantage to this standard VGA implementation is that the screen refresh operation requires a minimum of two sequential read operations per character since the ASCII value obtained by the first read is required to determine the address of the font line obtained in the second read.
The necessity for two reads is particularly painful for more recent systems which are pushing the cost and performance barriers. For example, higher resolution and/or higher refresh rate displays increase the pixel rate that must be sustained to maintain an image on the monitor. These pixel rates are already greater than the bandwidths that can be supported by simple accesses to DRAM, requiring the use of on-chip memory to buffer multiple reads that can take advantage of DRAM page mode operation. Even with the use of on-chip memory buffers, the limits of DRAM bandwidth are in sight.
Also, the bandwidth required for screen refresh reduces the bandwidth available for frame buffer accesses from the CPU. Graphics subsystem performance can be severely impacted as the available CPU bandwidth decreases. The issue of CPU bandwidth is a much greater concern in newer systems that seek to lower system cost by utilizing a single memory subsystem for both system memory and frame buffer. The screen refresh operation now steals bandwidth from system memory accesses as well as frame buffer accesses.
A traditional solution to reducing screen refresh bandwidth requirements has been to use Video RAM (VRAM) instead of DRAM. VRAM provides a separate serial port that can be used to provide pixel data to the monitor. Unfortunately, the serial port can only provide data from sequential locations in memory, making it impossible to perform the second read required to look up the font data.